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INTEGRATED CIRCUITS
DATA SHEET
TDA9855 I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Product specification Supersedes data of July 1994 File under Integrated Circuits, IC02 1997 Nov 04
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
FEATURES * Quasi alignment-free BTSC stereo decoder due to automatic adjustment of channel separation via I2C-bus * High integration level with automatically tuned integrated filters * Input level adjustment I2C-bus controlled * Alignment-free SAP processing * dbx noise reduction circuit * I2C-bus transceiver. GENERAL DESCRIPTION
TDA9855
The TDA9855 is a bipolar-integrated BTSC stereo/SAP decoder with hi-fi audio processor (I2C-bus controlled) for application in TV sets.
Audio processor * Selector for internal and external signals (line in) * Automatic volume level control * Subwoofer or surround output with separate volume control * Volume control * Special loudness characteristic automatically controlled in combination with volume setting * Bass and treble control * Audio signal zero-crossing detection between any volume step switching * Mute control at audio signal zero-crossing. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA9855 TDA9855WP SDIP52 PLCC68 DESCRIPTION plastic shrink dual in-line package; 52 leads (600 mil) plastic leaded chip carrier; 68 leads VERSION SOT247-1 SOT188-2
LICENSE INFORMATION A license is required for the use of this product. For further information, please contact COMPANY THAT Corporation BRANCH Licensing Operations ADDRESS 734 Forest St. Marlborough, MA 01752 USA Tel.: (508) 229-2500 Fax: (508) 229-2590 405 Palm House, 1-20-2 Honmachi Shibuya-ku, Tokyo 151 Japan Tel.: (03) 3378-0915 Fax: (03) 3374-5191
Tokyo Office
1997 Nov 04
2
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
QUICK REFERENCE DATA SYMBOL VCC ICC VCOMP(rms) VoR,L(rms) GLA cs THDL,R VI, O(rms) AVL Gc LB Gbass Gtreble Gs S/N PARAMETER supply voltage supply current input signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz CONDITIONS MIN. 8.0 50 - - - - 25 - 2 -15 -71 fi = 40 Hz fi = 40 Hz fi = 15 kHz fi = 40 Hz line out (mono); Vo = 0.5 V (RMS) CCIR noise weighting filter (peak value) DIN noise weighting filter (RMS value) audio section; Vo = 2 V (RMS); gain = 0 dB CCIR noise weighting filter (peak value) DIN noise weighting filter (RMS value) - - 94 107 - - 60 73 - -12 -12 -14 TYP. 8.5 75 250 500 4 -3.5 35 0.2 - - - 17 - - -
TDA9855
MAX. 9.0 95 - - - - - - - +6 +16 - +16.5 +12 +14 - -
UNIT V mA mV mV dB dB dB % V dB dB dB dB dB dB dB dBA
output signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz input level adjustment control stereo channel separation total harmonic distortion L + R signal handling (RMS value) control range volume control range maximum loudness boost bass control range treble control range subwoofer control range signal-to-noise ratio maximum gain maximum attenuation fL = 300 Hz; fR = 3 kHz fi = 1 kHz THD < 0.5%
- -
dB dBA
1997 Nov 04
3
1997 Nov 04
handbook, full pagewidth
External Input Right (EIR) C7 C10 C16 C6 C28 C12 44 (57) VIR 45 (58) 46 (59) 51 (67) 50 (66) 52 (68) C8 C9 LOR 36 (48) 37 (49) 38 (50) 41 39 (54) (51) 40 (52) 10 (14) 42 (55) 43 (56) LIR C45 C13 C14 C20 VCC C11 R2 R3 VOLUME RIGHT LOUDNESS CONTROL BASS RIGHT CONTROL TREBLE RIGHT CONTROL (63) 47 C36 OUTR (65) 49 C35
BLOCK DIAGRAM
Philips Semiconductors
C3
C4
C5
Q1
C2
R1
CERAMIC RESONATOR MURATA CSB503F58
31 (40)
32 (41)
33 (43)
34 (46)
35 (47)
STEREO DECODER
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
C1 INPUT SELECT EFFECTS AUTOMATIC VOLUME AND LEVEL CONTROL
COMP
29 (38)
INPUT LEVEL ADJUST
STEREO /SAP SWITCH
DEMATRIX + LINEOUT SELECT
TDA9855
(5) 4
C40 OUTS
ZERO CROSSING
4
DBX STEREO ADJUST SUPPLY LOGIC, I2CTRANCEIVER VOLUME LEFT LOUDNESS CONTROL (27) (24) (23) (22) (21) (20) 21 19 18 17 16 15 LOL C26 C15 C34 D1 MAD SDA SCL C30 C22 C23 C24 C25 C37 C27 C47 External Input Left (EIL) VCC C49 R5 LIL C29 (16) (19) 12 14 (18) (37) 13 28 (33, (39) (15) 34) 30 11 25 (6) 5 (35) (36) (13) 28 27 9 (12) 8 VIL C31 R4 C32 (11) 7 (3) 2
SUBWOOFER MATRIX, VOLUME SURROUND
SAP DEMODULATOR
BASS LEFT CONTROL
TREBLE LEFT CONTROL
(7) 6
C39 OUTL
(31) 24
(30) 23
(29) (25) 22 20
(4) 3
(1) 1
MHA837
R6
C33
R7
C17
C18
C19
C21
The numbers given in parenthesis refer to the TDA9855WP version.
Product specification
TDA9855
Fig.1 Block diagram.
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
Component list Electrolytic capacitors 20%; foil or ceramic capacitors 10%; resistors 5%; unless otherwise specified; see Fig.1. COMPONENTS C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C39 C40 1997 Nov 04 VALUE 10 F 470 nF 4.7 F 220 nF 10 F 2.2 F 4.7 F 15 nF 15 nF 2.2 F 8.2 nF 150 nF 33 nF 5.6 nF 100 F 4.7 F 4.7 F 100 nF 10 F 4.7 F 47 nF 1 F 1 F 10 F 10 F 2.2 F 2.2 F 4.7 F 2.2 F 8.2 nF 150 nF 33 nF 5.6 nF 100 F 150 nF 4.7 F 4.7 F 4.7 F 4.7 F 5 TYPE electrolytic foil electrolytic foil electrolytic electrolytic electrolytic foil foil electrolytic foil or ceramic foil foil foil or ceramic electrolytic electrolytic electrolytic foil electrolytic electrolytic foil electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic foil or ceramic foil foil foil or ceramic electrolytic foil electrolytic electrolytic electrolytic electrolytic 63 V 63 V 5% 63 V 63 V 63 V 10% 63 V 10% 16 V 63 V 63 V 10% 16 V 5% SMD 2220/1206 5% 5% 5% SMD 2220/1206 16 V 5% 16 V 16 V 16 V 16 V REMARK 63 V - 63 V - 63 V; Ileak < 1.5 A 16 V 16 V 5% 5% 63 V 5% SMD 2220/1206 5% 5% 5% SMD 2220/1206 16 V 63 V 63 V
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
COMPONENTS C45 C47 C49 D1 R1 R2 R3 R4 R5 R6 R7 Q1 VALUE 2.2 F 220 F 100 nF - 2.2 k 20 k 2.2 k 20 k 2.2 k 8.2 k 160 TYPE electrolytic electrolytic foil or ceramic - - - - - - - - CSB503F58 CSB503JF958 PINNING PINS SYMBOL PLCC68 TL n.c. B1L B2L OUTS MAD OUTL n.c. LDL VIL EOL CAV Vref LIL n.c. AVL SOL LOL CTW CTS CW CS VEO 1997 Nov 04 1 2 3 4 5 6 7 8 to 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SDIP52 1 - 2 3 4 5 6 - 7 8 9 10 11 12 - 13 14 15 16 17 18 19 20 6 treble control capacitor, left channel not connected bass control capacitor, left channel bass control capacitor, left channel DESCRIPTION
TDA9855
REMARK 16 V 25 V SMD 1206 general purpose diode - - - - - 2% 2% radial leads alternative as SMD
output subwoofer or output surround sound programmable address bit (module address) output, left channel not connected input loudness, left channel input volume control, left channel output effects, left channel automatic volume control capacitor reference voltage 0.5VCC input line, left channel not connected input automatic volume control, left channel output selector, left channel output line control, left channel capacitor timing wideband for dbx capacitor timing spectral for dbx capacitor wideband for dbx capacitor spectral for dbx variable emphasis output for dbx
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
PINS SYMBOL PLCC68 n.c. VEI n.c. CNR CM CDEC n.c. AGND DGND GND SDA SCL VCC COMP VCAP CP1 CP2 n.c. CPH n.c. CADJ CER CMO CSS LOR SOR AVR n.c. LIR CPS2 CPS1 EOR VIR LDR n.c. OUTR n.c. SW 26 27 28 29 30 31 32 33 34 - 35 36 37 38 39 40 41 42 43 44, 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 to 62 63 64 65 SDIP52 - 21 - 22 23 24 - - - 25 26 27 28 29 30 31 32 - 33 - 34 35 36 37 38 39 40 - 41 42 43 44 45 46 - 47 48 49 not connected variable emphasis input for dbx not connected capacitor noise reduction for dbx capacitor mute for SAP capacitor DC-decoupling for SAP not connected analog ground digital ground ground serial data input/output (I2C-bus) serial clock input (I2C-bus) supply voltage composite input signal capacitor for electronic filtering of supply capacitor for pilot detector capacitor for pilot detector not connected capacitor for phase detector not connected capacitor for filter adjustment ceramic resonator capacitor DC-decoupling mono capacitor DC-decoupling stereo/SAP output line control, right channel output selector, right channel DESCRIPTION
TDA9855
input automatic volume control, right channel not connected input line control, right channel capacitor 2 pseudo function capacitor 1 pseudo function output effects, right channel input volume control, right channel input loudness, right channel not connected output, right channel not connected filter capacitor for subwoofer
1997 Nov 04
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Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
PINS SYMBOL PLCC68 B2R B1R TR 66 67 68 SDIP52 50 51 52 bass control capacitor, right channel bass control capacitor, right channel treble control capacitor DESCRIPTION
TDA9855
MAD
67 B1R
66 B2R
B2L
B1L
handbook, full pagewidth
63 OUTR
OUTS
OUTL
n.c.
n.c.
n.c.
64 n.c.
62 n.c.
n.c. 10 LDL 11 VIL 12 EOL 13 CAV 14 Vref 15 LIL 16 n.c. 17 AVL 18 SOL 19 LOL 20 CTW 21 CTS 22 CW 23 CS 24 VEO 25 n.c. 26
61 n.c.
65 SW
68 TR
9
8
7
6
5
4
3
2
1
TL
60 n.c. 59 LDR 58 VIR 57 EOR 56 CPS1 55 CPS2 54 LIR 53 n.c.
TDA9855H
52 AVR 51 SOR 50 LOR 49 CSS 48 CMO 47 CER 46 CADJ 45 n.c. 44 n.c.
VEI 27
n.c. 28
CNR 29
CM 30
CDEC 31
n.c. 32
AGND 33
DGND 34
SDA 35
SCL 36
VCC 37
COMP 38
VCAP 39
CP1 40
CP2 41
n.c. 42
CPH 43
MHA836
Fig.2 Pin configuration (PLCC version).
1997 Nov 04
8
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
FUNCTIONAL DESCRIPTION Decoder INPUT LEVEL ADJUSTMENT
TDA9855
handbook, halfpage
TL B1L B2L OUTS MAD OUTL LDL VIL EOL
1 2 3 4 5 6 7 8 9
52 TR 51 B1R 50 B2R 49 SW 48 n.c. 47 OUTR 46 LDR 45 VIR 44 EOR 43 CPS1 42 CPS2 41 LIR 40 AVR
The composite input signal is fed to the input level adjustment stage. In order to compensate tolerances of the FM demodulator which supplied the composite input signal, the TDA9855 provides an input level adjustment stage. The control range is from -3.5 to +4.0 dB in steps of 0.5 dB. The subaddress control 3 of Tables 5 and 6 and the level adjust setting of Table 22 allows an optimum signal adjustment during the set alignment in the production line. This value has to be stored in a non-volatile memory. The maximum input signal voltage is 2 V (RMS). STEREO DECODER The output signal of the level adjustment stage is coupled to a low-pass filter which suppresses the baseband noise above 125 kHz. The composite signal is then fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The main L + R signal passes a 75 s fixed de-emphasis filter and is fed into the dematrix circuit. The decoded sub-signal L - R is sent to the stereo/SAP switch. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator. The stereo channel separation can be adjusted by an automatic procedure or manually. For a detailed description see Section "Adjustment procedure". The stereo identification can be read by the I2C-bus (see Table 2). Two different pilot thresholds can be selected via the I2C-bus (see Table 24). SAP DEMODULATOR The composite signal is fed from the output of the input level adjustment stage to the SAP demodulator circuit through a 5fH (fH = horizontal frequency) band-pass filter. The demodulator level is automatically controlled. The SAP demodulator includes internal noise and field strength detectors that mute the SAP output in the event of insufficient signal conditions. The SAP identification signal can be read by the I2C-bus (see Table 2). SWITCH The stereo/SAP switch feeds either the L - R signal or the SAP demodulator output signal via the internal dbx noise reduction circuit to the dematrix/line out select circuit. Table 21 shows the different switch modes provided at the output pins LOR and LOL.
CAV 10 Vref 11 LIL 12 AVL 13
TDA9855
SOL 14 LOL 15 CTW 16 CTS 17 CW 18 Cs 19 VEO 20 VEI 21 CNR 22 CM 23 CDEC 24 GND 25 SDA 26
MHA835
39 SOR 38 LOR 37 CSS 36 CMO 35 CER 34 CADJ 33 CPH 32 CP2 31 CP1 30 VCAP 29 COMP 28 VCC 27 SCL
Fig.3 Pin configuration (SDIP version).
1997 Nov 04
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Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
dbx DECODER The circuit includes all blocks required for the noise reduction system in accordance with the BTSC system specification. The output signal is fed through a 73 s fixed de-emphasis circuit to the dematrix block. INTEGRATED FILTERS The filter functions necessary for stereo and SAP demodulation and part of the dbx filter circuits are provided on-chip using transconductor circuits. The required filter accuracy is attained by an automatic filter alignment circuit. Audio processor SELECTOR The selector allows selecting either the internal line out signals LOR or LOL (dematrix output) or the external line in signals LIR and LIL and combines the left and right signals in several modes (see Table 12). The input signal capability of the line inputs (LIR/LIL) is 2 V (RMS). The output of the selector is AC-coupled to the automatic volume level control circuit via pins SOR/SOL and AVR/AVL to avoid offset voltages. AUTOMATIC VOLUME LEVEL CONTROL The automatic volume level stage controls its output voltage to a constant level of typically 200 mV (RMS) from an input voltage range of 0.1 to 1.1 V (RMS). The circuit adjusts variations in modulation during broadcasting and due to changes in the programme material. The function can be switched off. To avoid audible `plops' during the permanent operation of the AVL circuit a soft blending scheme has been applied between the different gain stages. A capacitor (4.7 F) at pin CAV determines the attack and decay time constants. In addition the ratio of attack and decay time can be changed via the I2C-bus (see notes 7 and 8 of Chapter "Characteristics"). EFFECTS The audio processor section offers the following mode selections: linear stereo, pseudo stereo, spatial stereo and forced mono.The spatial mode provides an antiphase crosstalk of 30% or 52% (switchable via the I2C-bus; see Table 18). VOLUME/LOUDNESS The volume control range is from +16 dB to -71 dB in steps of 1 dB and ends with a mute step (see Table 8). Balance control is achieved by the independent volume 1997 Nov 04 10 TREBLE CONTROL
TDA9855
control of each channel. The volume control blocks operate in combination with the loudness control. The filter is linear when maximum gain for volume control is selected. The filter characteristic changes automatically over a range of 28 dB down to a setting of -12 dB. At -12 dB volume control the maximum loudness boost is obtained. The filter characteristic is determined by external components. The proposed application provides a maximum boost of 17 dB for bass and 4.5 dB for treble. The loudness may be switched on or off via I2C-bus control (see Table 14). The left and right volume control stages include two independent zero-crossing detectors. In the zero-crossing mode a change in volume is automatically activated but not executed. The execution is enabled at the next zero-crossing of the signal. If a new volume step is activated before the previous one has been processed, the previous value will be executed first, and then the new value will be activated. If no zero-crossing occurs the next volume transmission will enforce the last activated volume setting. The zero-crossing mode is realized between adjoining steps and between any steps, but not from any step to mute. In this case the GMU bit is required for use. In case only one channel has to be muted, two steps are necessary. The first step is a transmission of any step to -71 dB and the second step is the -71 dB step to mute mode. The step of -71 dB to mute mode has no zero-crossing but this is not relevant. This procedure has to be provided by software. BASS CONTROL A single external 33 nF capacitor for each channel in combination with a linear operational amplifier and internal resistors provides a bass control range of +16.5 to -12 dB in steps of 1.5 dB at low frequencies (40 Hz). Internally the basic step width is 3 dB, with intermediate steps obtained by a toggle function that provides an additional 1.5 dB boost or attenuation (see Table 9). It should be noted that both loudness and bass control together result in a maximum bass boost of 34.5 dB for low volume steps.
The adjustable range of the treble control stage is from -12 to +12 dB in steps of 3 dB. The filter characteristic is determined by an external 5.6 nF capacitor for each channel. The logic circuitry is arranged in a way that the same data words (06H to 16H) can be used for both tone controls if a bass control range from -12 to +12 dB and a treble control range from -12 to +12 dB with 3 dB steps are used (see Tables 9 and 10).
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SUBWOOFER; SURROUND SOUND CONTROL The subwoofer or the surround mode can be activated with the control bit SUR (see Table 6). A low bit provides an output signal 12(L + R) in subwoofer mode, a high bit selects surround mode and provides an output signal 1 (L - R). The signal is fed through a volume control stage 2 with a range from +14 to -14 dB in 2 dB steps on top of the main channel control to the output pin OUTS. The last setting is the mute position (see Table 11). The capacitor C35 at pin SW provides a 230 Hz low-pass filter in subwoofer mode. In surround mode this capacitor should be disconnected. If balance is not in mid position the selected left and right output levels will be combined. MUTE The mute function can be activated independently with the last step of volume or subwoofer/surround control at the left, right or centre output. By setting the general mute bit GMU via the I2C-bus all audio part outputs are muted. All channels include an independent zero-crossing detector. The zero-crossing mute feature can be selected via bit TZCM: TZCM = 0: forced mute with direct execution TZCM = 1: execution in time with signal zero-crossing. In the zero-crossing mode a change of the GMU bit is activated but not executed. The execution is enabled at the next zero-crossing of the signal. To avoid a large delay of mute switching, when very low frequencies are processed, or the output signal amplitude is lower than the DC offset voltage, the following I2C-bus transmissions are needed: A first transmission for mute execution A second transmission approximately 100 ms later, which must switch the zero-crossing mode to forced mute (TZCM = 0) A third transmission to reactivate the zero-crossing mode (TZCM = 1). This transmission can take place immediately, but must follow before the next mute execution. Adjustment procedure COMPOSITE INPUT LEVEL ADJUSTMENT Apply the composite signal (from the FM demodulator) with 100% modulation (25 kHz deviation) L + R; fi = 300 Hz. Set input level control via the I2C-bus monitoring line output (500 mV 20 mV). Store the setting in a non-volatile memory. Adjustment of the spectral and
TDA9855
wideband expander is performed via the stereo channel separation adjust. AUTOMATIC ADJUSTMENT PROCEDURE * Capacitors of external inputs EIL and EIR must be grounded * Composite input signal L = 300 Hz, R = 3.1 kHz, 14% modulation for each channel; volume gain +16 dB via the I2C-bus; to avoid annoying sound level set GMU bit to logic 1 during adjustment procedure * Effects, AVL, loudness off * Selector setting SC0, SC1 and SC2 = 0, 0, 0 (see Table 12) * Line out setting bits: STEREO = 1, SAP = 0 (see Table 21) * Start adjustment by transmission ADJ = 1 in register ALI3; the decoder will align itself * After 1 second, stop alignment by transmitting ADJ = 0 in register ALI3 read the alignment data by an I2C-bus read operation from ALR1 and ALR2 (see Chapter "I2C-bus protocol") and store it in a non-volatile memory; the alignment procedure overwrites the previous data stored in ALI1 and ALI2 * Disconnect the capacitors of external inputs from ground. MANUAL ADJUSTMENT Manual adjustment is necessary when no dual tone generator is available (e.g. for service). * Spectral and wideband data have to be set to 10000 (middle position for adjustment range) * Composite input L = 300 Hz; 14% modulation * Adjust channel separation by varying wideband data * Composite input L = 3 kHz; 14% modulation * Adjust channel separation by varying spectral data * Iterative spectral/wideband operation for optimum adjustment * Store data in non-volatile memory. After every power-on, the alignment data and the input level adjustment data must be loaded from the non-volatile memory. TIMING CURRENT FOR RELEASE RATE Due to possible internal and external spreading, the timing current can be adjusted via the I2C-bus (see Table 25) as recommended by dbx. 11
1997 Nov 04
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Requirements for the composite input signal to ensure correct system performance SYMBOL PARAMETER CONDITIONS measured at pin COMP MIN. 162 TYP. 250
TDA9855
MAX. 363
UNIT mV
COMPL+R(rms) composite input level for 100% modulation L + R; 25 kHz deviation; fi = 300 Hz; RMS value COMP composite input level spreading under operating conditions output impedance low frequency roll-off high frequency roll-off total harmonic distortion L + R
Tamb = -20 to +70 C; aging; power supply influence note 1 25 kHz deviation L + R; -2 dB 25 kHz deviation L + R; -2 dB fi = 1 kHz; 25 kHz deviation fi = 1 kHz; 125 kHz deviation; note 2
-0.5
-
+0.5
dB
Zo flf fhf THDL,R
- - 100 - -
low-ohmic 5 - - - - 5 - 0.5 1.5
k Hz kHz % %
S/N
signal-to-noise ratio L + R/noise
CCIR 468-2 weighted quasi peak; L + R; 25 kHz deviation; fi = 1 kHz; 75 s de-emphasis critical picture modulation with sync only 44 54 - - - - - - dB dB dB
SB
side band suppression mono into unmodulated SAP carrier; SAP carrier/side band spectral spurious attenuation L + R/spurious
mono signal: 25 kHz deviation, 46 fi = 1 kHz; side band: SAP carrier frequency 1 kHz 50 Hz to 100 kHz; 40 mainly n x fH; no de-emphasis; L + R; 25 kHz deviation, f = 1 kHz as reference
SP
-
-
dB
Notes 1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by Zo and the composite input impedance (see Chapter "Characteristics", Section INPUT LEVEL ADJUSTMENT CONTROL) must be taken into account. 2. In order to prevent clipping at over-modulation (maximum deviation in the BTSC system for 100% modulation is 73 kHz).
1997 Nov 04
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Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC Vn Tamb Tstg Vesd supply voltage voltage of all other pins with respect to pin GND operating ambient temperature storage temperature electrostatic handling note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1.5 k. 2. Charge device model: C = 200 pF; R = 0 . THERMAL CHARACTERISTICS SYMBOL Rth(j-a) SOT247-1 SOT188-2 PARAMETER thermal resistance from junction to ambient CONDITIONS in free air 43 38 VALUE PARAMETER CONDITIONS 0 0 -20 -65 -2000 -300 MIN.
TDA9855
MAX. 9.5 VCC +70 +150 +2000 +300 V V
UNIT
C C V V
UNIT K/W K/W
1997 Nov 04
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Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
CHARACTERISTICS All voltages are measured relative to GND; VCC = 8.5 V; source resistance Rs 600 ; output load RL 10 k; CL 2.5 nF; AC-coupled; fi = 1 kHz; Tamb = 25 C; volume gain control Gc = 0 dB; bass linear; treble linear; loudness off; AVL off; effects linear; composite input signal in accordance with BTSC standard; see Fig.1; unless otherwise specified. SYMBOL General VCC ICC VDC supply voltage supply current DC voltage at signal handling pins 8.0 50 - 8.5 75
1 2VCC
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
9.0 95 -
V mA V
Decoder section INPUT LEVEL ADJUSTMENT CONTROL GLA Gstep Vi(rms) Zi input level adjustment control step resolution maximum input voltage level (RMS value) input impedance maximum gain maximum attenuation - - - 2 29.5 input level adjusted via I2C-bus - (L + R; fi = 300 Hz); monitoring line out - 4.0 -3.5 0.5 - 35 - - - - 40.5 - dB dB dB V k
STEREO DECODER MPXL+R(rms) input voltage level for 100% modulation L + R; 25 kHz deviation (RMS value) MPXL-R input voltage level for 100% modulation L - R; 50 kHz deviation (peak value) maximum headroom for L + R, fmod < 15 kHz; THD < 15% for L, R 75 s equivalent input modulation 250 mV
707
-
mV
MPX(max)
9
-
-
dB
MPXpilot(rms) nominal stereo pilot voltage level (RMS value) STon(rms) SToff(rms) hys OUTL+R pilot threshold voltage stereo on (RMS value) pilot threshold voltage stereo off (RMS value) hysteresis output voltage level for 100% modulation L + R at LINE OUT (L + R; fi = 300 Hz); monitoring LINE OUT input level adjusted via I2C-bus data STS = 1 data STS = 0 data STS = 1 data STS = 0
- - - 15 10 - 480
50 - - - - 2.5 500
- 35 30 - - - 520
mV mV mV mV mV dB mV
1997 Nov 04
14
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL cs PARAMETER stereo channel separation L/R at LINE OUT CONDITIONS aligned with dual tone 14% modulation; see Section "Adjustment procedure" in Chapter "Functional description" fL = 300 Hz; fR = 3 kHz fL = 300 Hz; fR = 8 kHz fL = 300 Hz; fR = 10 kHz fL, R L, R frequency response 14% modulation; fref = 300 Hz L or R fi = 50 Hz to 11 kHz fi = 12 kHz THDL,R S/N total harmonic distortion L, R at LINE OUT signal-to-noise ratio modulation L or R 1% to 100%; fi = 1 kHz mono mode; CCIR 468-2 weighted; quasi peak; 500 mV output signal -3 - - 50 - -3 0.2 60 25 20 15 35 30 25 MIN. TYP.
TDA9855
MAX.
UNIT
- - -
dB dB dB
- - 1.0 -
dB dB % dB
STEREO DECODER, OSCILLATOR (VCXO); note 1 fo fof fH nominal VCXO output frequency (32fH) spread of free-running frequency capture range frequency (nominal pilot) with nominal ceramic resonator with nominal ceramic resonator - 500.0 190 503.5 - 265 - 507.0 - kHz kHz Hz
SAP DEMODULATOR; note 2 SAPi(rms) SAPon(rms) SAPoff(rms) SAPhys SAPLEV nominal SAP carrier input voltage level (RMS value) pilot threshold voltage SAP on (RMS value) pilot threshold voltage SAP off (RMS value) hysteresis SAP output voltage level at LINE OUT LINE OUT (LOL, LOR) in position SAP/SAP; fmod = 300 Hz; 100% modulation 14% modulation; 50 Hz to 8 kHz; fref = 300 Hz fi = 1 kHz 15 kHz frequency deviation of intercarrier - - 35 - - 150 - - 2 500 - 85 - - - mV mV mV dB mV
fres THD
frequency response total harmonic distortion
-3 -
- 0.5
- 2.0
dB %
1997 Nov 04
15
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL PARAMETER CONDITIONS - 9 - 5 - 100% modulation; fi = 1 kHz; L or R; line out switched to SAP/SAP 100% modulation; fi = 1 kHz; SAP; line out switched to stereo 250 Hz to 6.3 kHz 50 MIN. TYP.
TDA9855
MAX. - - 120 - 2.5 -
UNIT
LINE OUT AT PINS LOL AND LOR Vo(rms) HEADo Zo VO RL CL ct nominal output voltage (RMS value) output headroom output impedance DC output voltage output load resistance output load capacitance idle crosstalk L, R into SAP 100% modulation 500 - 80 - - - mV dB k nF dB
0.45VCC 0.5VCC
0.55VCC V
idle crosstalk SAP into L, R
50
-
-
dB
VST-SAP
output voltage difference if switched from L, R to SAP
-
-
3
dB
dbx NOISE REDUCTION CIRCUIT tadj stereo adjustment time see Section "Adjustment procedure" in Chapter "Functional description" Is can be measured at pin 17 (pin 22) via current meter connected to 12VCC + 1 V 7 steps via I2C-bus - - 1 s
Is
nominal timing current for nominal release rate of spectral RMS detector spread of timing current timing current adjustment range timing current for release rate of wideband RMS detector nominal RMS detector release rate
-
24
-
A
Is Is(range) It Relrate
- - - nominal timing current and external capacitor values wideband spectral - -
- 30
1 3Is
15 - -
% % A
125 381
- -
dB/s dB/s
1997 Nov 04
16
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL Audio part CIRCUIT SECTION FROM PINS LIL AND LIR TO PINS OUTL, OUTR AND OUTS; note 3 B roll-off frequencies C6, C7, C10, C26, C27 and C29 = 2.2 F; Zi = Zi(min) low frequency (-3 dB) high frequency (-0.5 dB) THD total harmonic distortion Vi = 1 V (RMS); Gc = 0 dB; AVL on Vi = 2 V (RMS); Gc = 0 dB; AVL on Vi = 1 V (RMS); Gc = 0 dB; AVL off Vi = 2 V (RMS); Gc = 0 dB; AVL off PSRR B Vno power supply ripple rejection crosstalk between bus inputs and signal outputs noise output voltage Vr(rms) < 200 mV; fi = 100 Hz notes 4 and 5 CCIR 468-2 weighted; quasi peak measured in dBA cs channel separation Vi = 1 V; fi = 1 kHz Vi = 1 V; fi = 12.5 kHz SELECTOR (FROM PINS LOL, LOR, LIL AND LIR TO PINS SOL AND SOR) Zi s Vi(rms) Voffset input impedance input isolation of one selected source to any other input maximum input voltage (RMS value) DC offset voltage at selector output by selection of any inputs output impedance output load resistance (AC) output load capacitance voltage gain, selector f = 1 kHz; Vi = 1 V f = 12.5 kHz; Vi = 1 V THD < 0.5% 16 86 80 2 - 20 96 96 2.3 - - 20 - - - - 47 - - - 75 75 - - 0.2 0.2 0.05 0.02 50 110 40 8 - - PARAMETER CONDITIONS MIN. TYP.
TDA9855
MAX.
UNIT
20 - 0.5 0.5 - - - - 80 - - - 24 - - - 25
Hz kHz % % % % dB dB V V dB dB
k dB dB V mV
Zo RL CL Gc
- 5 - -
80 - - 0
120 - 2.5 -
k nF dB
1997 Nov 04
17
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9855
MAX.
UNIT
AUTOMATIC VOLUME LEVEL CONTROL (AVL) Zi Vi(rms) Gv Gstep input impedance maximum input voltage (RMS value) gain, maximum boost maximum attenuation equivalent step width between the input stages (soft switching system) input level at maximum boost (RMS value) input level at maximum attenuation (RMS value) Vo(rms) VDC(OFF) output level in AVL operation (RMS value) DC offset between different gain steps see Fig.4 see Fig.4 see Fig.4 voltage at pin CAV 6.50 to 6.33 V or 6.33 to 6.11 V or 6.11 to 5.33 V or 5.33 to 2.60 V; note 6 AT1 = 0; AT2 = 0; note 7 AT1 = 1; AT2 = 0; note 7 AT1 = 0; AT2 = 1; note 7 AT1 = 1; AT2 = 1; note 7 Idec spat1 spat2 Zi Zo RL CL Vi(rms) Vno charge current for decay time EFFECT CONTROLS anti-phase crosstalk by spatial effect phase shift by pseudo-stereo see Fig.5 - - - 8.0 - 5 - THD < 0.5% CCIR 468-2 weighted; quasi peak Gc = 16 dB Gc = 0 dB mute position - - - 110 33 10 220 50 - V V V 2.0 52 30 - 10.0 80 - - 2.15 - - - 12.0 120 - 2.5 - % % - k k nF V THD < 0.2% 8.8 2 5 14 - 11.0 - 6 15 1.5 13.2 - 7 16 - k V dB dB dB
Vi(rms)
- - 160 -
0.1 1.125 200 -
- - 250 6
V V mV mV
Ratt
discharge resistors for attack time constant
340 590 0.96 1.7
420 730 1.2 2.1 2.0
520 910 1.5 2.6 2.4
k k A
normal mode; CCD = 0; note 8 1.6
VOLUME TONE CONTROL PART (INPUT PINS VIL AND VIR TO PINS OUTX AND OUTS) volume input impedance output impedance output load resistance (AC) output load capacitance maximum input voltage (RMS value) noise output voltage
1997 Nov 04
18
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL Gc Gstep PARAMETER total continuous control range step resolution step error between any adjoining step Ga Gt m VDC(OFF) attenuator set error gain tracking error mute attenuation DC step offset between any adjacent step DC step offset between any step to mute LOUDNESS CONTROL PART LB maximum loudness boost loudness on; referred to loudness off; boost is determined by external components; see Fig.6 fi = 40 Hz fi = 10 kHz BASS CONTROL (see Fig.7) Gbass Gstep bass control maximum boost maximum attenuation step resolution step error between any adjoining step VDC(OFF) DC step offset between any adjacent step fi = 40 Hz fi = 40 Hz fi = 40 Hz 15.5 11 - - - 16.5 12 1.5 - - - - 17 4.5 Gc = +16 to 0 dB Gc = 0 to -71 dB Gc = +16 to +1 dB Gc = 0 to -71 dB Gc = +16 to -50 dB Gc = -51 to -71 dB Gc = +16 to -50 dB CONDITIONS maximum boost maximum attenuation - - - - - - - 80 - - - - MIN. 16 71 1 - - - - - 0.2 - 2 1 TYP.
TDA9855
MAX. - - - 0.5 2 3 2 - 10.0 5 15 10
UNIT dB dB dB dB dB dB dB dB mV mV mV mV
- - 17.5 13 - 0.5 15
dB dB
dB dB dB dB mV
TREBLE CONTROL (see Fig.8) Gtreble treble control maximum boost maximum attenuation maximum boost Gstep step resolution step error between any adjoining step VDC(OFF) DC step offset between any adjacent step fi = 15 kHz fi = 15 kHz fi > 15 kHz fi = 15 kHz 11 11 - - - - 12 12 - 3 - - 13 13 15 - 0.5 10 dB dB dB dB dB mV
1997 Nov 04
19
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9855
MAX.
UNIT
SUBWOOFER OR SURROUND CONTROL Gs subwoofer control maximum boost; fi = 40 Hz maximum attenuation; fi = 40 Hz Gstep m VDC(OFF) step resolution mute attenuation DC step offset between any adjacent step DC step offset between any step to mute Gs = 0 to +14 dB Gs = 0 to -14 dB 12 12 - 60 - - 14 14 2 - - - - 16 16 - - 10 5 15 dB dB dB dB mV mV mV
Gs = +2 to +14 dB without - input offset (pin SW connected to Vref) Gs = +2 to +14 dB inclusive offset from OUTR, OUTL Gs = 0 to -14 dB - - 4
- - 5
50 10 6
mV mV k
RF
internal resistor for low-pass filter with external capacitor at pin SW common mode rejection in surround sound at pin OUTS mono signal at VIL/VIR; f = 1 kHz; Vi = 1 V; balance = 0 dB
L + RREJ
26
36
-
dB
MUTING AT POWER SUPPLY DROP FOR OUTL, OUTR AND OUTS VCC-DROP VRESET(STA) supply drop for mute active - increasing supply voltage decreasing supply voltage VRESET(END) end of reset voltage Digital part (I2C-bus pins); note 10 VIH VIL IIH IIL VOL HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current LOW-level output voltage IIL = 3 mA 3 -0.3 -10 -10 - - - - - - VCC +1.5 +10 +10 0.4 V V A A V increasing supply voltage - 4.2 5.2 VCAP - 0.7 - - 5 6 2.5 5.8 6.8 V
POWER-ON RESET; note 9 start of reset voltage V V V
1997 Nov 04
20
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Notes to the characteristics
TDA9855
1. The oscillator is designed to operate together with a MURATA resonator CSB503F58 for TDA9855. Change of the resonator supplier is possible, but the resonator specification must be close to CSB503F58 for TDA9855. 2. The internal SAP carrier level is determined by the composite input level and the level adjustment gain. 3. Select in to input line control. V bus(p-p) 4. Crosstalk: 20 log -------------------V o(rms) 5. The transmission contains: a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics b) Clock frequency = 50 kHz c) Repetition burst rate = 400 Hz d) Maximum bus signal amplitude = 5 V (p-p). 6. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, -6 dB and -15 dB. 7. Attack time constant = CAV x Ratt.
- G v2 -Gv1 ----------- -----------20 20 C AV x 0.76 V 10 - 10 Decay time = ---------------------------------------------------------------------------------I dec
8.
Example: CAV = 4.7 F; Idec = 2 A; Gv1 = -9 dB; Gv2 = +6 dB decay time results in 4.14 s. 9. When reset is active the GMU-bit (general mute) and the LMU-bit (LINE OUT mute) is set and the I2C-bus receiver is in the reset position. 10. The AC characteristics are in accordance with the I2C-bus specification. The maximum clock frequency is 100 kHz. Information about the I2C-bus can be found in the brochure "The I2C-bus and how to use it" (order number 9398 393 40011).
1997 Nov 04
21
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
I2C-BUS PROTOCOL I2C-bus format to read (slave transmits data) S Table 1 SLAVE ADDRESS R/W A DATA MA
TDA9855
DATA
P
Explanation of I2C-bus format to read (slave transmits data) NAME DESCRIPTION START condition; generated by the master 101 101 1 pin MAD not connected 101 101 0 pin MAD connected to ground logic 1 (read); generated by the master acknowledge; generated by the slave slave transmits an 8-bit data word acknowledge; generated by the master STOP condition; generated by the master Definition of the transmitted bytes after read condition MSB FUNCTION BYTE D7 D6 SAPP SAPP D5 STP STP D4 A14 A24 D3 A13 A23 D2 A12 A22 D1 A11 A21 D0 A10 A20 ALR1 ALR2 Y Y LSB
S Standard SLAVE ADDRESS Pin programmable SLAVE ADDRESS R/W A DATA MA P Table 2
Alignment read 1 Alignment read 2 Table 3
Function of the bits in Table 2 BITS FUNCTION stereo pilot identification (stereo received = 1) SAP pilot identification (SAP received = 1) stereo alignment read data for wideband expander for spectral expander indefinite
STP SAPP A1X to A2X A1X A2X Y
The master generates an acknowledge when it has received the first data word ALR1, then the slave transmits the next data word ALR2. Afterwards the master generates an acknowledge, then the slave begins transmitting the first data word ALR1 etc. until the master generates no acknowledge and transmits a STOP condition.
1997 Nov 04
22
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
I2C-bus format to write (slave receives data) S Table 4 SLAVE ADDRESS R/W A SUBADDRESS A DATA
TDA9855
A
P
Explanation of I2C-bus format to write (slave receives data) NAME DESCRIPTION START condition 101 101 1 pin MAD not connected 101 101 0 pin MAD connected to ground logic 0 (write) acknowledge; generated by the slave see Table 5 see Table 6 STOP condition
S Standard SLAVE ADDRESS Pin programmable SLAVE ADDRESS R/W A SUBADDRESS (SAD) DATA P
If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of Table 5 is performed. Table 5 Subaddress second byte after slave address MSB FUNCTION Volume right Volume left Bass Treble Subwoofer Control 1 Control 2 Control 3 Alignment 1 Alignment 2 Alignment 3 REGISTER D7 VR VL BA TR SW CON1 CON2 CON3 ALI1 ALI2 ALI3 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 0 D3 0 0 0 0 0 0 0 0 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 D1 0 0 1 1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 1 0 1 0 00 01 02 03 04 05 06 07 08 09 0A LSB HEX
1997 Nov 04
23
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Table 6 Definition of third byte after slave address MSB FUNCTION Volume right Volume left Bass Treble Subwoofer Control 1 Control 2 Control 3 Alignment 1 Alignment 2 Alignment 3 Table 7 REGISTER D7 VR VL BA TR SW CON1 CON2 CON3 ALI1 ALI2 ALI3 0 0 0 0 0 GMU SAP 0 0 STS ADJ D6 VR6 VL6 0 0 0 AVLON STEREO 0 0 0 AT1 D5 VR5 VL5 0 0 SW5 LOFF TZCM 0 0 0 AT2 D4 VR4 VL4 BA4 TR4 SW4 X VZCM 0 A14 A24 0 D3 VR3 VL3 BA3 TR3 SW3 SUR LMU L3 A13 A23 1 D2 VR2 VL2 BA2 TR2 SW2 SC2 EF2 L2 A12 A22 TC2
TDA9855
LSB D1 VR1 VL1 BA1 TR1 0 SC1 EF1 L1 A11 A21 TC1 D0 VR0 VL0 BA0 0 0 SC0 EF0 L0 A10 A20 TC0
Function of the bits in Table 6 BITS FUNCTION volume control right volume control left bass control treble control subwoofer, surround control mute control for outputs OUTL, OUTR and OUTS (generate mute) AVL on/off switch loudness on/off don't care bit surround/subwoofer SUR = 1 12(L - R); SUR = 0 12(L + R) selection between line in and line out mode selection for line out zero-crossing mode in mute operation (treble and subwoofer/surround output stage) zero-crossing mode in volume operation mute control for dematrix + line out select selection between mono, stereo linear, spatial stereo and pseudo mode input level adjustment stereo adjustment on/off stereo alignment data for wideband expander stereo alignment data for spectral expander attack time at AVL timing current alignment data stereo level switch
VR0 to VR6 VL0 to VL6 BA0 to BA4 TR1 to TR3 SW2 to SW5 GMU AVLON LOFF X SUR SC0 to SC2 STEREO, SAP TZCM VZCM LMU EF0 to EF2 L0 to L3 ADJ A1X A2X AT1 and AT2 TC0 to TC2 STS
1997 Nov 04
24
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Table 8 Gc (dB) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 1997 Nov 04 Volume setting in registers VR and VL DATA D6 V6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D5 V5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 D4 V4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 D3 V3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 25 D2 V2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 D1 V1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 V0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
TDA9855
HEX 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
DATA Gc (dB) -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59 -60 1997 Nov 04 D6 V6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 V5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 V4 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 V3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 26 D2 V2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D1 V1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D0 V0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
TDA9855
HEX 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
DATA Gc (dB) -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 Mute Table 9 D6 V6 0 0 0 0 0 0 0 0 0 0 0 0 D5 V5 1 1 1 1 1 1 1 1 1 1 1 1 D4 V4 1 1 1 0 0 0 0 0 0 0 0 0 D3 V3 0 0 0 1 1 1 1 1 1 1 1 0 D2 V2 0 0 0 1 1 1 1 0 0 0 0 1 D1 V1 1 0 0 1 1 0 0 1 1 0 0 1 D0 V0 0 1 0 1 0 1 0 1 0 1 0 1
TDA9855
HEX 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27
Bass setting in register BA DATA
Gbass (dB) 16.5 15.0 13.5 12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0
D4 BA4 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
D3 BA3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
D2 BA2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1
D1 BA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D0 BA0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
HEX 19 18 17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06
1997 Nov 04
27
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Table 10 Treble setting in register TR DATA Gtreble (dB) 12 9 6 3 0 -3 -6 -9 -12 D4 TR4 1 1 1 1 0 0 0 0 0 D3 TR3 0 0 0 0 1 1 1 1 0 D2 TR2 1 1 0 0 1 1 0 0 1 D1 TR1 1 0 1 0 1 0 1 0 1 FUNCTION(1) HEX 16 14 12 10 0E 0C 0A 08 06 Inputs LOR and LOL Inputs LOR and LOR Inputs LOL and LOL Inputs LOL and LOR Inputs LIR and LIL Inputs LIR and LIR Inputs LIL and LIL Inputs LIL and LIR Note D2 SC2 0 0 0 0 1 1 1 1
TDA9855
Table 12 Selector setting in register CON1 DATA D1 SC1 0 0 1 1 0 0 1 1 D0 SC0 0 1 0 1 0 1 0 1
Table 11 Subwoofer/surround setting in register SW DATA Gs (dB) 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 Mute D5 SW5 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D4 SW4 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D3 SW3 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D2 SW2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 HEX 3C 38 34 30 2C 28 24 20 1C 18 14 10 0C 08 04 00
1. Input connected to outputs SOR and SOL. Table 13 SUR bit setting in register CON1 FUNCTION Surround sound Subwoofer Table 14 LOFF bit setting in register CON1 CHARACTERISTIC With loudness Linear DATA D5 0 1 DATA D3 1 0
Table 15 AVLON bit setting in register CON1 FUNCTION Automatic volume control off Automatic volume control on DATA D6 0 1
1997 Nov 04
28
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Table 16 Mute setting in register CON1 FUNCTION Forced mute at OUTR, OUTL and OUTS Audio processor controlled outputs Table 17 Mute setting in register CON2 FUNCTION Forced mute at LOR and LOL Stereo processor controlled outputs Table 18 Effects setting in register CON2 DATA FUNCTION Stereo linear on Pseudo on Spatial stereo; 30% anti-phase crosstalk Spatial stereo; 50% anti-phase crosstalk Forced mono D2 EF2 0 0 0 0 1 D1 EF1 0 0 1 1 1
TDA9855
DATA D7 GMU 1 0
DATA D3 LMU 1 0
D0 EF0 0 1 0 1 1
Table 19 Zero-crossing detection setting in register CON2 FUNCTION Direct mute control Mute control delayed until the next zero-crossing Table 20 Zero-crossing detection setting in register CON2 FUNCTION Direct volume control Volume control delayed until the next zero-crossing DATA D4 VZCM 0 1 DATA D5 TZCM 0 1
1997 Nov 04
29
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Table 21 Switch setting at line out LINE OUT SIGNALS AT LOL SAP Mute Left Mono Mono Mono Mono LOR SAP mute right mono SAP mute mono DATA TRANSMISSION STATUS INTERNAL SWITCH, READABLE BITS IN REGISTER ALR1, ALR2: D6 (SAPP), D5 (STP) SAP received no SAP received STEREO received no STEREO received SAP received no SAP received independent
TDA9855
SETTING BITS IN REGISTER CON2 D7 SAP 1 1 0 0 1 1 0 D6 STEREO 1 1 1 1 0 0 0
Table 22 Input level adjust setting in register CON3 DATA Gl (dB) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 D3 L3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 L2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 L1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 L0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 HEX 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00
1997 Nov 04
30
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
Table 23 Alignment data for expander in read register ALR1 and ALR2 and in write register ALI1 and ALI2 DATA FUNCTION Gain increase D4 AX4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Nominal gain Gain decrease 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 AX3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 AX2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 AX1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 AX0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Table 24 STS bit setting in register ALI2 (pilot threshold stereo on) FUNCTION STon(rms) 35 mV STon(rms) 30 mV DATA D7 1 0
1997 Nov 04
31
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Table 25 Timing current setting in register ALI3 DATA IS RANGE +30% +20% +10% Nominal -10% -20% -30% D2 TC2 1 1 1 0 0 0 0 D1 TC1 0 0 1 1 1 0 0 D0 TC0 0 1 0 1 0 1 0 Table 27 ADJ bit setting in register ALI3 FUNCTION Stereo decoder operation mode Auto adjustment of channel separation
TDA9855
DATA D7 0 1
Table 26 AVL attack time setting in register ALI3 DATA Ratt () 420 730 1200 2100 D6 AT1 0 1 0 1 D5 AT2 0 0 1 1
MHA312
handbook, full pagewidth
300
7
(1)
Vo(rms) (mV) 250
VCAV (V) 6
(2)
5 200
(3)
4
160 3
2
100 10-2 (1) VCAV (2) Vo max(rms) (3) Vo min(rms)
VI(rms) (V) AVL measured at pin EOL/EOR. Y1 axis output level in AVL operation with typically 200 mV. Y2 axis VCAV DC voltage at pin CAV corresponds with typical gain steps in range of +6 to -15 dB.
10-1
1 1 10
Fig.4 Automatic volume level control diagram.
1997 Nov 04
32
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
MHA311
handbook, full pagewidth
0
phase (degree) -100
(1)
(2) (3)
-200
-300
-400 10
102
103
104
f (Hz)
105
(1) see Table 28. (2) see Table 28. (3) see Table 28.
Fig.5 Pseudo (phase in degrees) as a function of frequency (left output).
Table 28 Explanation of curves in Fig.5 CURVE 1 2 3 CAPACITANCE AT PIN CPS1 (nF) 15 5.6 5.6 CAPACITANCE AT PIN CPS2 (nF) 15 47 68 EFFECT normal intensified more intensified
1997 Nov 04
33
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
handbook, full pagewidth
25
MHA844
15
16 14 9
5
4 -1
-5
-6 -11 -16
-15
-21 -26
-25
-31 -36
-35
10
20
102
103
f (Hz)
104
Fig.6 Volume control with loudness (including low roll-off frequency).
handbook, full pagewidth
21
MHA843
18 Gbass (dB) 15 12 9 6 3 0 -3 -6 -9 -12 -15 10 20 102 103 104
f (Hz)
Fig.7 Bass control.
1997 Nov 04
34
parameter: volume gain setting (dB)
Gc (dB)
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
handbook, full pagewidth
15
MHA845
12 Gtreble (dB) 9 6 3 0 -3 -6 -9 -12 -15 102
200
103
104
f (Hz)
105
Fig.8 Treble control.
handbook, halfpage
60
MHA842
noise (V) 40
20
0 -80
-60
-40
-20
0 gain (dBA)
20
Fig.9 Noise as function of gain in dBA (RMS value).
1997 Nov 04
35
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
handbook, full pagewidth
gain volume = 16 dB (Gv(max)) LIL LIR
TDA9855
POWER STAGE G = 20 dB P(max) = 40 W at 4
VI = 200 mV; AVL off or VI = 100 to 1250 mV; AVL on
VO = 1.26 V for P(max) 4 dB margin for power peaks
MHA841
All values given are in RMS value.
Fig.10 Level diagram.
1997 Nov 04
36
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
APPLICATION HINTS Selection of input signals by using the zero-crossing mute mode (see Fig.11)
TDA9855
A selection between the internal signal path and the external input LIL/LIR produces a modulation click depending on the difference of the signal values at the time of switching. At t1 the maximum possible difference between signals is 7 V (p-p) and gives a large click. Using the zero-crossing detector no modulation click is audible. For example: The selection is enabled at t1, the microcontroller sets the zero-crossing bit (TZCM = 1) and then the mute bit (GMU = 1) via the I2C-bus. The output signal follows the input A signal, until the next zero-crossing occurs and then activates mute. After a fixed delay time before t2, the microcontroller has to send the forced mute mode (TZCM = 0) and the return to the zero-crossing mode (TZCM = 1) to be sure that mute is enabled. The output signal remains muted until the next signal zero-crossing of input B occurs, and then follows that signal. The delay time t2 - t1 is e.g. 40 ms. The zero-crossing function is working at the lowest frequency of 40 Hz.
handbook, full pagewidth
V 4 3 2 1 0 -1 -2 -3 -4
(2) (1)
MED436
t1
t2
(3)
t
(1) Input A (internal signal). (2) Output. (3) Input B (external input signal).
Fig.11 Zero-crossing function; only one channel shown.
1997 Nov 04
37
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Loudness filter calculation example Figure 12 shows the basic loudness circuit with an external low-pass filter application. R1 allows an attenuation range of 21 dB while the boost is determined by the gain stage V1. Both result in a loudness control range of +16 to -12 dB. Defining fref as the frequency where the level does not change while switching loudness on/off. The external resistor R3 for fref can be calculated as: 10 R3 = R1 -------------------- . With Gv = -21 dB and R1 = 33 k, G 1 - 10 R3 = 3.2 k is generated. For the low-pass filter characteristic the value of the external capacitor C1 can be determined by setting a specific boost for a defined frequency and referring the gain to Gv at fref as indicated above. ( R1 + R3 ) x 10 - R3 1 -------------------- = ------------------------------------------------------------Gv j ( C1 ) -----20 1 - 10 For example: 3 dB boost at f = 1 kHz Gv = Gv(ref) + 3 dB = -18 dB; f = 1 kHz and C1 = 100 nF. If a loudness characteristic with additional high frequency boost is desired, an additional high-pass section has to be included in the external filter circuit as indicated in the block diagram. A filter configuration that provides AC coupling avoids offset voltage problems. Figure 13 shows an example of the loudness circuit with bass and treble boost.
handbook, halfpage 220 nF
TDA9855
handbook, halfpage C
KVL
VIX R1 33 k LOX C1 R3
V1
Gv -----20
R2
-----20
v
MHA838
Fig.12 Basic loudness circuit.
Gv -----20
VIX R1 33 k LOX
8.2 nF 20 k
V1
150 nF 2.2 k
R2
MHA839
Fig.13 Loudness circuit with bass and treble boost.
1997 Nov 04
38
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
handbook, full pagewidth
VP VCC 8.5 V 4.7 k 470 F
+8.5 V to oscilloscope
28 inputs 12 6 outputs to oscilloscope 2 x 4.7 F 100 F 2 x 5 k
MHA840
TDA9855
41 2 x 220 nF 2 x 600 25 11 100 F 30 47
Fig.14 Turn-on/off power supply circuit diagram.
handbook, full pagewidth
10
MED433
(V) 8
(1) 6
4 (2)
2
0 0 (1) VCC. (2) VO. 1 2 3 4 t (s) 5
Fig.15 Turn-on/off behaviour.
1997 Nov 04
39
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
INTERNAL PIN CONFIGURATIONS The pin numbers refer to the SDIP-version.
TDA9855
handbook, halfpage handbook, halfpage 4.25 V
1 +
+ 3.64 k
4.25 V
2 +
2.4 k
7.79 k
4.25 V
MHA846 MHA847
Fig.16 Pin 1: treble control capacitor, left; pin 52: treble control capacitor, right.
Fig.17 Pin 2: bass control capacitor input, left; pin 51: bass control capacitor input, right.
handbook, halfpage
+
3 4.25 V
handbook, halfpage
+
4 4.25 V
80
80
MHA848
MHA849
Fig.18 Pin 3: bass control capacitor output, left; pin 50: bass control capacitor output, right.
Fig.19 Pin 4: output subwoofer; pin 6: output, left channel; pin 14: output selector, left channel; pin 39: output selector, right channel; pin 47: output, right channel.
1997 Nov 04
40
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
handbook, halfpage
5 +
1.8 k
MHA850
Fig.20 Pin 5: MAD (I2C-bus address switch).
handbook, halfpage
7 4.25 V + 1.33 k
MHA851
Fig.21 Pin 7: input loudness, left; pin 46: input loudness, right.
handbook, halfpage
8 4.25 V + 10.58 k 4.8 k
MHA852
Fig.22 Pin 8: input volume, left; pin 45: input volume, right.
1997 Nov 04
41
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
handbook, halfpage
+
9 4.25 V
handbook, halfpage
10 +
15 k
6.8 k
MHA854
MHA853
Fig.23 Pin 9: output effects, left; pin 44: output effects, right.
Fig.24 Pin 10: automatic volume control capacitor.
handbook, halfpage
11 +
handbook, halfpage
12 4.25 V +
3.4 k
3.4 k 20 k
MHA855
20 k
MHA856
Fig.25 Pin 11: reference voltage 0.5VCC.
Fig.26 Pin 12: line input, left; pin 41: line input, right.
1997 Nov 04
42
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
handbook, halfpage
4.25 V 13 1 +
handbook, halfpage
+
15 4.25 V
2
5 k
3 1.75 k
MHA858
8
MHA857
Fig.27 Pin 13: input automatic volume control, left; pin 40: input automatic volume control, right.
Fig.28 Pin 15: line output, left; pin 38: line output, right.
handbook, halfpage
16 +
handbook, halfpage
18 4.25 V +
6 k
MHA859
MHA860
Fig.29 Pin 16: timing capacitor wideband for dbx; pin 17: timing capacitor spectral for dbx.
Fig.30 Pin 18: capacitor wideband for dbx; pin 19: capacitor spectral for dbx.
1997 Nov 04
43
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
handbook, halfpage
+
20
handbook, halfpage
+
21
600
MHA861 MHA862
Fig.31 Pin 20: variable emphasis out for dbx.
Fig.32 Pin 21: variable emphasis in for dbx.
handbook, halfpage handbook, halfpage
22 4.25 V +
+
23
10 k
MHA863 MHA864
Fig.33 Pin 22: capacitor noise reduction for dbx.
Fig.34 Pin 23: capacitor mute for SAP.
handbook, halfpage
+
24 4.25 V
handbook, halfpage
26 5 V 1.8 k
20 k
20 k
MHA865
MHA866
Fig.35 Pin 24: capacitor DC decoupling for SAP.
Fig.36 Pin 26: SDA (I2C-bus data input/output).
1997 Nov 04
44
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
handbook, halfpage
5 V 27 1.8 k
handbook, halfpage
28 apply 8.5 V to this pin
MHA867
MHA868
Fig.37 Pin 27: SCL (I2C-bus clock).
Fig.38 Pin 28: supply voltage.
handbook, halfpage
29 4.25 V +
handbook, halfpage
+
30
4.7 k
300
5 k 30 k
MHA869 MHA870
Fig.39 Pin 29: input composite signal.
Fig.40 Pin 30: smoothing capacitor for supply.
handbook, halfpage
+
handbook, halfpage
32 4.25 V
31 4.25 V +
3.5 k 3.5 k
MHA871
3.5 k
MHA872
Fig.41 Pin 31: capacitor for pilot detector.
Fig.42 Pin 32: capacitor for pilot detector.
1997 Nov 04
45
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
handbook, halfpage
33 4.25 V +
handbook, halfpage
34 +
10 k
10 k
MHA873 MHA874
Fig.43 Pin 33: capacitor for phase detector.
Fig.44 Pin 34: capacitor for filter adjust.
handbook, halfpage
35 +
handbook, halfpage
36 4.25 V +
3 k
MHA875
10 k
10 k
MHA876
Fig.45 Pin 35: ceramic resonator.
Fig.46 Pin 36: capacitor DC decoupling mono; pin 37: capacitor DC decoupling stereo/SAP.
handbook, halfpage
4.25 V 49 1
handbook, halfpage
+
43 4.25 V
+
2
3 15 k
MHA877
10 k
10 k
Fig.47 Pin 43: capacitor 1 pseudo function; pin 42: capacitor 2 pseudo function.
8
MHA878
Fig.48 Pin 49: capacitor subwoofer.
1997 Nov 04
46
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
PACKAGE OUTLINES SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
TDA9855
SOT247-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 wM (e 1) MH b 52 27
pin 1 index E
1
26
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 47.9 47.1 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT247-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-01-22 95-03-11
1997 Nov 04
47
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9855
PLCC68: plastic leaded chip carrier; 68 leads
SOT188-2
eD y 60 61 X 44 43 Z E A
eE
bp b1 wM
68
1
pin 1 index e
E
HE A A4 A1 (A 3)
k
9
27
k1
Lp detail X
10 e D HD
26 ZD B
vM A
vMB 0 5 scale 10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm inches
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30 0.13
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07
45 o
0.180 0.020 0.01 0.165
0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT188-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1997 Nov 04
48
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. PLCC REFLOW SOLDERING Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9398 510 63011). 1997 Nov 04 49
TDA9855
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9855
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Nov 04
50
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
NOTES
TDA9855
1997 Nov 04
51
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/03/pp52
Date of release: 1997 Nov 04
Document order number:
9397 750 02446

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